DAC 2012: Atrenta to automate production of power-intent constraints
Atrenta is working on an architectural-level power-planning tool that will automatically generate power-intent constraints in UPF (Guide) or CPF format. The unannounced product is meant to help...
View ArticleClik here to view.
Mentor zooms in on power peaks with emulator interface
Mentor Graphics has developed a software interface for its Veloce emulators that lets third-party tools fetch logic-activity information from running tasks for faster and more accurate power...
View ArticleDocea adds API to model power software interactions
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to let engineering teams see how chipset designs would fare under a variety of...
View ArticleTwo-day app challenge results in RTL power analyzer
For DAC 2015 in San Francisco Invionics set itself the challenge of taking suggestions for an EDA tool on Monday that its developers could implement using the company’s custom-tool framework by 2pm...
View ArticleMulticore Association to update performance-estimation standard
A contribution from software-parallelization specialist Silexica is helping to update the Multicore Association’s Software/Hardware Interface for Multicore/Manycore (SHIM) standard. Version 1.0 of...
View Article
